Date of Award

Fall 12-4-2015

Level of Access Assigned by Author

Campus-Only Thesis

Degree Name

Master of Computer Engineering (MCompE)

Department

Electrical and Computer Engineering

Advisor

Yifeng Zhu

Second Committee Member

Bruce Segee

Third Committee Member

Vincent Weaver

Abstract

Phase Change Memory (PCM) is an emerging nonvolatile memory technology that offers high storage density, byte-addressability, fast access speed, and low standby power. These characteristics make PCM a promising alternative to slow Hard disk drives (HDD). Since PCM’s performance is close to DRAM, PCM can be directly connected to processors via the memory bus and accessed using load/ store instructions. However, PCM has a limited write endurance (10 7 - 10 8 writes per cell), which makes it unreliable for storage because most of the storage workloads contain significant data and metadata overwrites. This thesis has proposed and implemented a reliability-oriented buffer caching with the collaboration of TLB, page table and page fault handler to reduce data write traffic to PCM.

One of the challenges is synchronous and frequent update of metadata, which deceases the lifetime of metadata blocks much quicker than data blocks. By leveraging byte addressability, this thesis has implemented a state-of-the-art wear leveling algorithm (called start-gap) to reduce the lifetime cost caused by frequent metadata updates. This thesis has applied the start-gap algorithm at the inode granularity.

We have simulated the reliability-oriented buffering and the start-gap algorithm under four real world storage server traces. The simulation results show that a small size of buffer cache can reduce the data write traffic significantly by absorbing over-writes, and wear leveling can effectively reduce the issue of write endurance caused by frequent metadata update.

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