Date of Award

5-2004

Level of Access Assigned by Author

Campus-Only Thesis

Degree Name

Master of Science (MS)

Department

Electrical and Computer Engineering

Advisor

Donald M. Hummels

Second Committee Member

David E. Kotecki

Third Committee Member

Allison I. Whitney

Abstract

This thesis provides a novel continuous calibration technique for pipelined Analog-to- Digital Converters (ADCs). The new scheme utilizes an existing digital calibration algorithm and extends it to work in real-time. The goal is to digitally calibrate pipelined ADCs in the background without interrupting the normal operation of the converter. The concept behind the digital calibration algorithm is described and simulated using a 1-bit per stage pipeline architecture. Dominant static error mechanisms present in pipeline architectures are identified and discussed. These errors are successfully corrected by the implemented digital calibration algorithm. The calibration scheme is transparent to the overall system performance and is demonstrated using a 14-bit ADC with I-bit per stage architecture and 16 identical stages. The first seven stages in the pipeline are calibrated. Continuous calibration is realized using a hardware description language (Verilog HDL) and two extra stages located at the end of the pipeline. The extra stages are only used during the calibration process. Verilog implementations of stage and error correction logic, as well as a finite state machine to control the calibration process are presented. The real-time digital calibration technique is verified and successfully demonstrated using simulation results obtained in MATLAB and the Verilog-XL simulator.

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