Date of Award

5-2006

Level of Access

Campus-Only Dissertation

Degree Name

Doctor of Philosophy (PhD)

Department

Electrical and Computer Engineering

Advisor

David E. Kotecki

Second Committee Member

Donald M. Hummels

Third Committee Member

Richard O. Eason

Abstract

Recently reported double heterojunction bipolar transistor (DHBT) devices manufactured in Indium Phosphide (InP) technology with ft and fmax both over 300 GHz enable advanced high-speed digital and mixed-signal circuits. In this thesis, the use of InP DHBT devices for high-speed accumulator circuits and X– and Ku–band direct digital synthesizer (DDS) circuits are investigated. At these frequencies, new technological challenges in the design of digital and mixed-signal circuits arise in areas including power consumption and clock distribution. This thesis addresses the speed/power tradeoffs in high-speed accumulator designs, the design of DDS circuits, and clock distribution simulation. The results of six accumulator circuits and two DDS circuits are reported as part of this thesis. The fastest 4-bit accumulator at a 41 GHz clock rate is reported, as well as the fastest DDS circuits operating at 13 GHz and 32 GHz clock rates. The 13 GHz DDS has a worst case spurious-free dynamic range (SFDR) of 26.67 dBc and consumes 5.42 W of power, while the 32 GHz DDS has a worst case SFDR of 21.56 dBc and consumes 9.45 W of power. In addition to the circuit designs, a methodology for simulating electrically long clock interconnects and a new figure of merit for comparing DDS designs are developed.

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