Date of Award


Level of Access

Campus-Only Thesis

Degree Name

Master of Science (MS)


Electrical and Computer Engineering


David E. Kotecki

Second Committee Member

Donald M. Hummels

Third Committee Member

Richard O. Eason


An increasing demand for multi-GHz direct digital synthesizers has prompted research for high-speed phase to amplitude converters. A high-speed read-only memory (ROM) look-up table operating at 20-40 GHz range clock frequency can be used as a high-speed phase to amplitude converter. A 16x6-bit ROM, employing an architecture suitable for use as a phase to amplitude converter for DDS, has been implemented in InP double heterojunction bipolar transistor (DHBT) technology. The ROM uses a -3.8 V power supply and dissipates 1.13 W of power. The ROM is implemented in a test circuit that includes an 8-bit accumulator and a 6-bit digital to analog converter (DAC) to facilitate demonstration of high-speed operation. The maximum operating clock frequency is measured to be 36 GHz. To increase the bit size of the ROM two 32x6-bit ROMs were designed. The first 32x6-bit ROM is designed for low power consumption; the second 32x6-bit ROM is designed to operate at maximum clock frequency. The schematic simulation results showed these ROMs operated at 20GHz and 46GHz clock frequency respectively. The low power design consumes 1.95 W and high-speed design consumes 7.07 W of power.