Date of Award
Level of Access Assigned by Author
Master of Science (MS)
Electrical and Computer Engineering
David E. Kotecki
Second Committee Member
Donald M. Hummels
Third Committee Member
Richard O. Eason
Advanced Silicon-Germanium (SiGe) Bipolar and Complimentary Metal Oxide Semiconductor (BiCMOS) manufacturing processes require novel circuit design methodology to achieve high performance. The SiGe process leverages existing 120nm silicon process advancements, but lower device breakdown voltages require new circuits to achieve low voltage operation. The SiGe heterojunction bipolar transistors (HBTs) with an ft over 200GHz allow for high speed bipolar junction technology (BJT) logic blocks combined with high density and low power CMOS logic. This thesis presents the design of a digital accumulator operating at 19GHz with a 1.2Volt supply consuming only 466mW of power. This architecture applies a modified differential pair logic family called the triple tail cell to construct logic circuit with no stacked gates between the supplies. A folded logic technique is used to collapse logic that would normally be constructed from stacked differential pairs into parallel single stacked logic that is later recombined.
Bethel, Ryan H., "Low Voltage BiCMOS Circuit Topologies for the Design of a 19GHz, 1.2V, 4-Bit Accumulator in Silicon-Germanium" (2007). Electronic Theses and Dissertations. 963.