Jianhui Yue

Date of Award

12-2012

Level of Access Assigned by Author

Campus-Only Dissertation

Degree Name

Doctor of Philosophy (PhD)

Department

Computer Engineering

Advisor

Yifeng Zhu

Second Committee Member

Bruce Segee

Third Committee Member

Richard Eason

Abstract

Buffer cache replacement schemes play an important role in conserving memory energy. Conventional algorithms only aim to maximize cache hit rates and ignore the current power status of memory chips. This thesis studies new cache replacement algorithms to optimize the trade-off between cache hit rates and energy consumption. It is observed that the interplay among the following three important factors appears to be the most important: hit rates, clustering ability and the populating schemes to allocate buffers. Based on this important observation, a new buffer management scheme is proposed to cluster indirect and data blocks into separate sets of memory chips to achieve better energy efficiency. In addition, four generic power-aware replacement algorithms are proposed to manage the cache. Upon a cache miss for a block of a file, choose a victim block from (1) the most recently accessed memory chip and (2) the memory chip that holds the largest number of recently accessed blocks.

This thesis also exploits a new storage technology, phase change memory (PCM), to improve the I/O performance and energy efficiency. Due to better scalability than DRAM and no refresh power, PCM is emerging as a promising memory alternative and complementation to DRAM. However, its slow write is a challenge. Parallel Chip PCM (PC2M) is proposed to re-architect PCM to speed up write and micro-writes is proposed to cancel the write on a finer granularity to block less reads. Motivated by the PCM asymmetric properties, the two-stage write strategy is proposed to write all 0 bits first and then write all 1 bits. The adaptive bit-inverse scheme is proposed to improve the previous one. In addition, by exploiting the subarray-level parallelism, two new power management schemes, called PASAK and WAVAK, are proposed to fully overlap a write operation with read operations at different subarrays inside a bank. PASAK accurately estimate power requirement of each access and judiciously schedule requests. WAVAK further improves PASAK by conditionally invert all bits in a write block to reduce energy requirements.

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